发明名称 Method to reduce variation in LDD series resistance
摘要 A process used to retard out diffusion of P type dopants from P type LDD regions, resulting in unwanted LDD series resistance increases, has been developed. The process features the formation of a nitrogen containing layer, placed between the P type LDD region and overlying silicon oxide regions, retarding the diffusion of boron from the LDD regions to the overlying silicon oxide regions, during subsequent high temperature anneals. The nitrogen containing layer, such as a thin silicon nitride layer, or a silicon oxynitride layer, formed during or after reoxidation of a P type polysilicon gate structure, is also formed in a region that also retards the out diffusion of P type dopants from the P type polysilicon gate structure.
申请公布号 US6534388(B1) 申请公布日期 2003.03.18
申请号 US20000670330 申请日期 2000.09.27
申请人 CHARTERED SEMICONDUCTOR MANUFACTURING LTD. 发明人 LIN WENHE;DONG ZHONG;CHOOI SIMON;PEY KIN LEONG
分类号 H01L21/336;H01L29/78;(IPC1-7):H01L21/04 主分类号 H01L21/336
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