| 摘要 |
A DRAM includes a memory cell array section where a number of bit lines are located periodically and densely, and a peripheral circuit section formed at the outside of the memory cell array section and adjacent to the memory cell array section. A half of the bit lines formed in the memory cell array section are pulled out from the memory cell array section into the peripheral circuit section and are located periodically but sparsely in the peripheral circuit section. In the peripheral circuit section, the half of the bit lines have a portion which has a line width "B" larger than the line width "A" of the bit lines in the memory cell array section, and which is separated from the memory cell array section by a predetermined distance on the order of a minimum standardized size "D". A line space "C" in the memory cell array section and the minimum standardized size "D" fulfill the relation of C<=D<=2xC.
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