发明名称 METHOD FOR FABRICATING SEMICONDUCTOR DEVICE USING PATTERN WITH 3-D STRUCTURE
摘要 PURPOSE: A method for fabricating a semiconductor device using pattern with 3-D structure is provided to produce a MOSFET and DRAM by performing the whole etch, selective etch and the whole deposition process repeatedly without any mask process, and also to produce a DRAM by above-mentioned processes. CONSTITUTION: A 3-D structure pattern is formed on a substrate(100) by pressing a cast or mold onto the prepared materials on the substrate. A device region is formed by reactive ion etching on the 3-D structure pattern and the insulating layer(102). After source electrode material and planarity layer are deposited in turn, they are entirely etched to form a n+ source electrode(108). A p+ channel region(110) and n+ drain electrode(112) are formed by the same etching process as that used in forming n+ source electrode. After forming a trench and then a metal wire repeatedly by performing the reactive ion etch, the whole etch, deposition and thermal processing, a source metal wire(116), gate metal wire(126), drain metal wire(128) are formed in turn.
申请公布号 KR20030022464(A) 申请公布日期 2003.03.17
申请号 KR20010055426 申请日期 2001.09.10
申请人 MINUTA TECHNOLOGY 发明人 KANG, DAL YEONG;LEE, HONG HUI
分类号 H01L21/334;(IPC1-7):H01L21/334 主分类号 H01L21/334
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