| 摘要 |
<p>PROBLEM TO BE SOLVED: To solve such problems on a synchronous high-speed memory that the setup time for write data is liable to run short and sometimes causes difficulty in no-wait operation. SOLUTION: This memory control circuit 1 has a memory input control circuit 4, a latch control circuit 3, a latch junction circuit 50, and a read data selection circuit 5. The latch function circuit 50 latches a write command, write data and an addresses under the control of the latch control circuit 3 and delays a write cycle being viewed from a memory 2 by one clock component. In this process, the write data can be made sufficiently ready. When there is read access to a memory address where write is not completed, the read data selection circuit 5 selects and outputs the write data latched by the latch function circuit 50.</p> |
