| 摘要 |
<p>PROBLEM TO BE SOLVED: To shorten a test time as mush as possible. SOLUTION: This device is provided with an address control circuit 20 having an address counter 22 outputting an inputted first block address for a first mode and outputting a second block address selected out of a block address space being double of a block address space corresponding to a plurality of main body blocks of a memory section having a plurality of main body blocks for a second mode, and a block selection control circuit 30 selecting a main body block corresponding to an output of the address counter when a value of the highest order of a block address being an output of the address counter is in a first logic level and selecting a redundant block instead of the main body block by making the main body block forced non-selection when a value of the highest order is in a second logic level at a test.</p> |
