发明名称 CLOCK SIGNAL GENERATING CIRCUIT AND CLOCK SIGNAL GENERATING METHOD
摘要 PROBLEM TO BE SOLVED: To simultaneously digital/analog-convert digital data of various sampling frequency by one circuit. SOLUTION: A USB interface 68 generates a reference signal corresponding to the reception of a SOF packet among received packets at the time of receiving voice digital data from a connected device, for example, a hard disk drive. A clock recovery circuit 113 generates a clock signal corresponding to a sampling frequency of 44.1 KHz and a clock signal corresponding to a sampling frequency of 48.0 KHz based on the reference signal supplied from the USB interface 68, and supplies the generated clock signal corresponding to the sampling frequency of 44.1 KHz and clock signal corresponding to the sampling frequency of 48.0 KHz to a digital audio interface.
申请公布号 JP2003078512(A) 申请公布日期 2003.03.14
申请号 JP20010268337 申请日期 2001.09.05
申请人 SONY CORP 发明人 HAGIMORI MASASHIGE
分类号 G06F13/38;G06F1/06;G06F13/42;H03L7/08;H04L7/033 主分类号 G06F13/38
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