发明名称 A PARALLEL COUNTER AND A LOGIC CIRCUIT FOR PERFORMING MULTIPLICATION
摘要 A logic circuit such as a parallel counter comprises logic for generating output bits as elementary symmetric functions of the input bits. The parallel counter can be used in a multiplication circuit. A multiplication circuit is also provided in which an array of combinations of each bit of a binary number with each other bit of another binary number is generated having a reduced form in order to reduce the steps required in array reduction.
申请公布号 WO0212995(A3) 申请公布日期 2003.03.13
申请号 WO2001GB03415 申请日期 2001.07.27
申请人 AUTOMATIC PARALLEL DESIGNS LIMITED;MEULEMANS, PETER;RUMYNIN, DMITRIY;TALWAR, SUNIL 发明人 MEULEMANS, PETER;RUMYNIN, DMITRIY;TALWAR, SUNIL
分类号 G06F7/53;G06F7/52;G06F7/60 主分类号 G06F7/53
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