| 摘要 |
A digital delay line (10) is provided for generating a digital output signal delayed with respect to a digital input signal. The digital delay line (10) comprises a plurality of delay elements (DLY1 to DLYN) arranged in series. The digital output signal is taken from the delay line at the final delay elements DLYN. The digital delay line (10) further comprises insertion control circuitry (15) which causes the digital input signal to be inserted selectively into the delay line at one of the delay elements DLYM preceding or the same as the final delay element DLYN. The insertion delay element is selected based on the desired delay between the input and output digital signals. |
