| 摘要 |
<p>A receiver for high bitrate binary signals (DI) contains a soft decision circuit with three parallel deciders (D1-D3) coupled to a 2:1 multiplexer (M). The three deciders (D1-D3) have different threshold values and generate four potential states. The 2:1 multiplexer (M) translates the four different states into a restored data signal (DO) and a reliability signal (D1) indicating the decision reliability. <IMAGE></p> |
