发明名称 |
Method to improve a testability analysis of a hierarchical design |
摘要 |
A method to improve the testability and analysis of a hierarchical semiconductor chip design formed from a plurality of macros, each macro identifying a particular portion of a semiconductor chip design. This method includes providing a first macro netlist that identifies a logical description of a first portion of the semiconductor chip design and performing RPT analysis on the first macro netlist. The method also includes providing a second macro netlist identifying a logical description of a second portion of the semiconductor chip design and performing an RPT analysis on the second macro netlist. The first macro netlist is combined with the second macro netlist and an RPT analysis is performed on the combination of the first and second macro netlists. |
申请公布号 |
US6532571(B1) |
申请公布日期 |
2003.03.11 |
申请号 |
US20000489240 |
申请日期 |
2000.01.21 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
GABRIELSON RICHARD M.;MCCAULEY KEVIN W.;RIZZOLO RICHARD F.;ROBBINS BRYAN J.;SWENTON JOSEPH M. |
分类号 |
G01R31/3183;(IPC1-7):G06F17/50;G01R31/28 |
主分类号 |
G01R31/3183 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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