HIGH SPEED SAMPLING RECEIVER

摘要

PURPOSE: To accelerate a latch operation by shortening a fall delay time of a latch in a sampling mode while making low power consumption. CONSTITUTION: Source electrodes of differentially connected NMOSs 13 and 14 with small amplitude data inputted from an external part are connected to input terminals 1 and 2 in common and grounded through an NMOS 11 for current supply. Drain electrodes of the NMOSs 13 and 14 are respectively connected to drain electrodes of an NMOS 17 and PMOSs 15 and 19, and drain electrodes of an NMOS 18 and PMOSs 16 and 20. A CMOS inverter type bistable circuit consists of the NMOSs 17 and 18 and the PMOSs 15 and 16, output terminals of the NMOSs 13 and 14 and an output terminal of the bistable circuit are parallelly connected, and their outputs (D and D*) are inputted to an RS-F/F circuit 50 constituting a slave latching part.