| 摘要 |
PROBLEM TO BE SOLVED: To enable the reduction of the development term of a semiconductor integrated circuit, regarding a layout method of a semiconductor integrated circuit using a cell needing the timing adjustment of an input signal like a D flip-flop cell. SOLUTION: As the D flip-flop cell which is one kind of cells needing the timing adjustment of the data D, a D flip-flop cell which can select, from the outside, one delay path out of four delay paths different in delay time by using signals SA, SB for delay adjustment is used as a unit cell.
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