FIFO MEMORY CONTROL CIRCUIT

摘要

PROBLEM TO BE SOLVED: To provide an FIFO memory control circuit capable of preventing transition to or falling into a wrong operating sequence due to incorrect data generated when the read control of an FIFO memory is in the transient state of starting up a device or by the influence of noise. SOLUTION: When the read-out control falls from the ATM layer side through a UTOPIA interface part 2, an RENB generating part 3 outputs an RENB signal in which 'L' block is 53 clock unit. A counter circuit in a read address generating part 4 for generating an RADR signal for conducting the read control to the FIFO memory part 1 operates only in the 'L' section of the RENB signal, and the read address generating part 4 adds the value of the RADR signal according to the phase of the readout RSOC signal. The read address generating part 4 outputs an SOC- MASK signal as a control signal to an SOC mask part 5 in order to mask an incorrect RSOC signal.