发明名称 Method and apparatus for reducing the number of programmed bits in a memory array
摘要 A memory system that reduces the number of memory cells programmed in a memory array is provided. A logic comparator determines whether more than half of the bits of a write data word require a program operation. If so, the logic comparator provides a status signal having a first state. A status signal having the first state causes the inverse of the write data word to be written to the memory array, along with the status signal. If the status signal does not have the first state, the write data word is written to the memory array, along with the status signal. During a read operation, a data word and corresponding status signal are read from the array. If the status signal has the first state, the inverse of the data word is provided as a read data word. Otherwise, the data word is provided as the read data word.
申请公布号 US2003046481(A1) 申请公布日期 2003.03.06
申请号 US20010898725 申请日期 2001.07.03
申请人 KUSHNARENKO ALEXANDER 发明人 KUSHNARENKO ALEXANDER
分类号 G11C7/22;G11C16/10;G11C16/26;(IPC1-7):G06F12/00;G06F13/00 主分类号 G11C7/22
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