AREA EFFICIENT PARALLEL TURBO DECODING

摘要

Turbo decoders may have large decoding latency and low throughput due to iterative decoding. One way to increase the throughput and reduce the latency of turbo decoders is to use high speed decoding schemes. In particular, area-efficient parallel decoding schemes may be used to overcome the decoding latency and throughput associated with turbo decoders. In addition, hybrid parallel decoding schemes may be used in high-level parallelism implementations. Moreover, the area-efficient parallel decoding schemes introduce little or no performance degradation by the concepts of a sliding window approach. Accordingly, a data block (400) is divided into sub-blocks or sliding windows (B1-B21). In addition, the data block is divided into P segments (401, 402, 403) where P represents the level of parallelism. Segment 401 decodes sub-blocks B1-B7, segment 402 decodes sub-blocks B8-B14, and segment 403 decodes sub-blocks B15-B21. Recursion operations for forward and bacward state metrics are performed in parallel on each segment (401, 402, 403) using the sliding window approach for each sub-block in the segment. A timing sequence (410) for the segment 402 is shown.