| 摘要 |
<p>Text Integrated circuit device (20) comprising a silicon substrate (21), integrated devices (22) with contacts (23.1, 23.2), an isolating layer (24) at least partially covering the integrated devices (22) and comprising conducting areas (24.1, 24.2) which establish a conductive path to the contacts (23.1, 23.2) of the integrated devices (22). A metallization level (25) with metal lines (26.1, 26.2, 26.3, 26.4) is provided which connect to one of the contacts (23.2). The metal lines (26.1, 26.2, 26.3, 26.4) are situated above the isolating layer (24). A passivation layer (27) - situated above the metallization level (25) - comprises at least two contact areas (28.1, 28.2) for partially exposing at least two of the metal lines (26.2, 26.4). A bump bridge (29) comprising a conductive, low-resistance material, is situated on the passivation layer (27). The bump bridge (29) has a high aspect ratio and provides for a conductive connection between at least two of the metal lines (26.2, 26.4). It crosses another metal line (26.3) that is situated within the metallization level (25), without making contact to this metal line (26.3), and a substantial part of the bump bridge (29) is supported by the passivation layer (27).</p> |
