| 摘要 |
Disclosed are methods and apparatus for sampling defects. A test chip having a plurality of test structures is provided that is designed so that defect sampling may be customized to obtain different critical areas from the test chip. Each test structure is conceptually divided into a plurality of unit cells (e.g., a pair of grounded and floating conductive lines) (602). The defects of a percentage of unit cells may then be sampled for each test structure to conceptually form a sub test structure that has a different size than the original test structure (604). The percentage of unit cells that are sampled for each test structure is chosen so as to achieve a specific critical area curve (606). The defects from each sampled set of unit cells may then combined to determine yield for a product chip having the same specific critical area curve (606, 608). In general terms, a first set of unit cells may be sampled from the test structures to predict yield for a product chip having a first critical area, and a second different set of unit cells may be sampled to predict yield for a product chip having a second critical area (602, 604). In other specific implementations, one or more test structure may have one or more attributes that affect systematic yield, as compared to random attributes which affect random yield.
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