| 摘要 |
A metal oxide semiconductor (MOS) device includes a silicon substrate, source and drain regions having a predetermined junction depth (dj) relative to the surface of the silicon substrate, and a gate region having a contoured channel region formed by a locally-oxidized silicon (LOCOS) structure grown to a predetermined thickness. The contoured channel region has a substantially flat surface, extending into the silicon substrate by a predetermined depth (dc), and contoured edges. The depth (dc) of the substantially flat surface of the contoured channel region is greater than or equal to the depth of the junction depth (dj) of the source and drain regions, such that the contoured channel region is lower than or equal to the source and drain regions relative to the surface of the silicon substrate. The lower depth of the contoured channel region relative to the source and drain regions decouples shallow junction requirements from the channel length scaling. The effectively elongated channel length allows easier device optimization. The contoured edges enable formation of a channel having a non-uniform doping profile, where the contoured edges have light doped regions. The lighter-doped regions interface with the source and drain regions, resulting in a more uniform electric field density that improves the electron hole mobility for PMOS circuits, and improves the mobility of electrons for NMOS circuits. The structure also reduces junction capacitances, and gate to source and drain overlap capacitances. Consequently, a more scalable and more reliable MOSFET device can be formed.
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