| 摘要 |
PURPOSE: A synchronous bit line sense amplifier is provided, which improves an operation speed by controlling a bit line sense amplifier operation time by synchronizing it to a clock signal. CONSTITUTION: According to the synchronous bit line sense amplifier, a command decoder unit(100) generates a row address(add) and a row active signal(BSENSE) synchronized to an external clock signal(CLK) by decoding a read command signal or a write command signal received from the external during a row active command. A row path control unit(200) generates a bank select signal(BK_SEL) and a word line enable signal(WL_N) to enable a word line of a memory cell array block by receiving the row active signal and the address signal from the command decoder unit. A bit line sense amplifier unit(300) senses cell data of the word line selected by the word line enable signal. A sense timing control unit(400) delays the row active signal from the command decoder unit, and generates a sense amplifier active signal(S_ACT) synchronized to a clock signal. And a block control unit(500) generates a signal(SS_BK) controlling an operation of the bit line sense amplifier unit by receiving the bank select signal of the row path control unit and the sense amplifier active signal of the sense timing control unit.
|
