发明名称 DIGITALLY CONTROLLED ANALOG DELAY LOCKED LOOP(DLL)
摘要 PROBLEM TO BE SOLVED: To provide a DLL circuit which has high resolution, a wide capture range and high speed synchronization. SOLUTION: The DDL circuit is provided with a first control signal generating means and a second control signal generating means. The first means has an analog delay line 114 and a digital control circuit 118, and coarsely adjusts a delay time of the analog delay line 114 by digital control, according to the phase difference between an input signal and a feed back signal. The second means adjusts the delay time finely and continuously.
申请公布号 JP2003060501(A) 申请公布日期 2003.02.28
申请号 JP20010372456 申请日期 2001.12.06
申请人 CYPRESS SEMICONDUCTOR CORP 发明人 FISCUS TIMOTHY E
分类号 H03L7/08;H03K5/00;H03K5/13;H03L7/081;H03L7/087 主分类号 H03L7/08
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