发明名称 |
Method of manufacturing semiconductor integrated circuit device having capacitor element |
摘要 |
In a complete CMOS SRAM having a memory cell composed of six MISFETs formed over a substrate, a capacitor element having a stack structure is formed of a lower electrode covering the memory cell, an upper electrode, and a capacitor insulating film (dielectric film) interposed between the lower electrode and the upper electrode. One electrode (the lower electrode) of the capacitor element is connected to one storage node of a flip-flop circuit, and the other electrode (the upper electrode) is connected to the other storage node. As a result, the storage node capacitance of the memory cell of the SRAM is increased to improve the soft error resistance.
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申请公布号 |
US2003038303(A1) |
申请公布日期 |
2003.02.27 |
申请号 |
US20020270193 |
申请日期 |
2002.10.15 |
申请人 |
HASHIMOTO NAOTAKA;HOSHINO YUTAKA;IKEDA SHUJI |
发明人 |
HASHIMOTO NAOTAKA;HOSHINO YUTAKA;IKEDA SHUJI |
分类号 |
G11C11/412;H01L21/8244;H01L23/522;H01L27/10;H01L27/11;(IPC1-7):H01L31/032 |
主分类号 |
G11C11/412 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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