LDMOS DEVICE WITH DOUBLE N-LAYERING AND PROCESS FOR ITS MANUFACTURE

摘要

The tradeoff between breakdown voltage and on-resistance for LDMOS devices has been improved by having two epitaxial N- regions instead of the single epitaxial N- region that is used by devices of the prior art. The resistivities and thicknesses of these two N- regions are chosen so that their mean resistivity is similar to that of the aforementioned single N- layer. A key feature is that the lower N- layer (i.e. the one closest to the P- substrate) has a resistivity that is greater than that of the upper N- layer. If these constraints are met, as described in greater detail in the specification, improvements in breakdown voltage of up to 60% can be achieved without having to increase the on-resistance. A process for manufacturing the device is also described.