| 摘要 |
A phase-locked loop (PLL) employs a ring oscillator for the voltage-controlled oscillator (VCO), and the ring oscillator comprises an odd number of inverting stages operating at a given frequency. The frequency of the ring oscillator is determined by the delay through each stage and the number of stages. The output signal of each stage has a phase determined by the number of stages, and each stage provides its output signal with a different phase. The VCO of the PLL selects phases of the ring oscillator to clock the counter of the feedback divider of the PLL. Each phase is selected by a multiplexer (mux) under the control of a finite state machine that monitors the output of the counter. When the counter completes a full count cycle on one phase of the ring oscillator, the finite state machine selects a different phase of the ring oscillator to clock the counter for the next count cycle. The phase selected advances or delays the start of the next count cycle by the delay of one or more stages of the ring oscillator. Thus, for a PLL having a three-stage ring oscillator and a mux selecting the phase from each stage sequentially (first to last) for every count cycle, the effective count of the counter is (V+1/3) or (N-1/3), as opposed to N, depending on whether the selected phase delays or advances the start of the next count cycle.
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