SYSTEM ARCHITECTURE OF A HIGH BIT RATE SWITCH MODULE BETWEEN FUNCTIONAL UNITS IN A SYSTEM ON A CHIP

摘要

The invention relates to a switch for a high bit rate transaction of data between master and slave devices in a system-on-a-chip (SOC) including a set of busses allowing maximum parallelism in said switch, a crossbar unit used to transfer data bursts from one of said devices to another of said devices, and connections to at least two said master devices which can originate read and write transactions of said data with any other master or slave and at least two said slave devices which can respond to read and write transactions of said data with any other master or slave. The switch transactions may be partial transfers or burst transfers. The switch crossbar may further comprise a byte enable mechanism for handling gaps in said write transactions of said data. The invention also describes a method for a high data rate transaction.