| 摘要 |
Data reception circuit for receiving a serial input data stream with a high data transfer rate, where the data reception circuit has a data stream separation circuit (4) for separating the serial input data stream into a plurality of separate data streams with a reduced data transfer rate, a reference clock signal generation circuit (13) for generating a reference clock signal whose clock frequency corresponds to the data transfer rate of the separate data streams, a delay circuit (12) having a delay element chain (27) which comprises a plurality of series-connected delay elements, the first delay element (27-1) in the delay element chain (27) receiving the generated reference clock signal, and each delay element outputting a delayed reference clock signal via a signal output (11) in the delay circuit (12), a first, asynchronously clocked register array (8) which comprises a plurality of register banks (26), each register bank (26) in the first register array (8) being asynchronously clocked by an associated separate data stream and reading in the delayed reference clock signals from the delay circuit (12) in order to buffer-store a signal change in the separate data stream, a second, synchronously clocked register array (17) which comprises a plurality of register banks (28), each register bank (28) in the second register array (17) being synchronously clocked by the reference clock signal and reading in and buffer-storing the register content of an associated register bank (26) in the first register array (8) and a synchronously clocked logic circuit (18) which evaluates the register content buffer-stored in the second register array (17) in order to reconstruct the serial input data stream.
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