Outputting bit error tables from semiconducting devices involves test control unit reading bit error table from memory unit on request from test arrangement and transferring to test arrangement

摘要

The method involves a test control unit (TE) in the semiconducting device (HE) reading the bit error table from a memory unit (SE) in the semiconducting device on request from a test arrangement (PA) and sequentially transferring the bit error table to the test arrangement. The semiconducting device can contain at least two similar memory devices, each with an associated test control unit. AN Independent claim is also included for an arrangement for outputting bit error tables from semiconducting devices.