发明名称 |
Cache memory system for network data storage system, comprises memory segment having respective parity segment and data segments |
摘要 |
A cache memory system (16) comprises multiple SDRAM memory boards including respective memory segments. The memory segments are grouped into parity sets having N respective segments containing a parity segment, and N-1 respective data segments. A data value stored in parity segment is calculated by a logical exclusive or operation of data value stored in data segments. An Independent claim is also included for cache memory system usage method.
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申请公布号 |
DE10236179(A1) |
申请公布日期 |
2003.02.20 |
申请号 |
DE20021036179 |
申请日期 |
2002.08.07 |
申请人 |
EMC CORP., HOPKINTON |
发明人 |
WALTON, JOHN K.;BERMINGHAM, MICHAEL;MACLELLAN, CHRISTOPHER S. |
分类号 |
G06F12/08;G06F3/06;G06F11/10;G06F12/16;G11C29/00;(IPC1-7):G06F12/16 |
主分类号 |
G06F12/08 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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