发明名称 |
Controlling signal states and leakage current during a sleep mode |
摘要 |
A circuit includes an input terminal, an output terminal and a latch. The input terminal receives an input signal. The latch is programmable with a value. The latch communicates the input signal to the output terminal in response to the circuit not being in a sleep mode and in response to the circuit being in the sleep mode, furnishes a second signal to the output terminal indicative of the value. |
申请公布号 |
AU2002320469(A1) |
申请公布日期 |
2003.02.17 |
申请号 |
AU20020320469 |
申请日期 |
2002.07.11 |
申请人 |
INTEL CORPORATION (A CORPORATION OF DELAWARE) |
发明人 |
JAMES FEDDELLER;ZAHID AHSANULLAH;MICHAEL LONGWELL |
分类号 |
H03K3/037;H03K17/22;H03K19/00;H03K19/0185 |
主分类号 |
H03K3/037 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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