| 摘要 |
<p>PROBLEM TO BE SOLVED: To reduce the cell area more than that of a twin MONOS cell and prevent the growth of conductive residues which are apt to short-circuit between word lines. SOLUTION: A memory cell has a first conductivity-type semiconductor step, two second conductivity-type semiconductor regions SBLi, SBLi+1 (i: natural number) functioning as the sources or drains and two mutually insulated memory gate electrodes (CGa or CGb, WL1) facing the sidewalls of the step, interposed with a gate dielectric film CS having charge-storing power. Two memory transistors are formed in three-dimesional form at the step and the cell area is very small. Since conductive wire sidewalls CGa, CGb exist on a base surface, when it is processed to form word lines, and hence conductive residues of the word lines hardly grow in cuts in its cutting process.</p> |
