发明名称 Signal delay time calculation method of semiconductor integrated circuit and computer program product for executing the method
摘要 In a signal delay time calculation method of calculating an approximate signal delay time in an LSI based on AWE in which a signal voltage waveform is calculated by using terms of an admittance up to n-th order obtained by Laplace transform for the LSI. Even if there are one or more poles of the signal having a real-number part of more than zero, it is determined to obtain a high-accuracy signal delay time when the delay time is obtained within a range to which those poles provide smaller effect.
申请公布号 US6519748(B2) 申请公布日期 2003.02.11
申请号 US20010895339 申请日期 2001.06.29
申请人 KABUSHIKI KAISHA TOSHIBA 发明人 SAKAMOTO TOSHIYUKI
分类号 G01R31/319;G06F17/50;H01L21/82;(IPC1-7):G06F17/50 主分类号 G01R31/319
代理机构 代理人
主权项
地址