Power semiconductor device structure with vertical PNP transistor

摘要

A power semiconductor device structure formed in a chip of semiconductor material includes an N-type substrate and an N-type epitaxial layer. The structure comprises a P-type insulation region which forms a pocket in which control circuitry is formed, and a plurality of fully insulated PNP power transistors. Each PNP power transistor comprises a P-type collector region including of a buried region between the substrate and the epitaxial layer and a contact region. The P region delimits a base N region within which an emitter P region is formed.