发明名称 |
Method and apparatus for defining signal timing for an integrated circuit device |
摘要 |
One embodiment of the present invention provides a system for defining signal timing for an integrated circuit device. The system operates by first creating a virtual timing reference plane for the integrated circuit device. A first signal line is then routed from a semiconductor die within the integrated circuit package to a first external connection of the integrated circuit package. Next, the system generates a first escape pattern for a first circuit trace on a printed circuit board from the first external connection to the virtual timing reference plane. This first escape pattern specifies a route from where the first external connection meets the printed circuit board to the virtual timing reference plane. Finally, the system establishes a first set of signal timings for a combination of the first signal line and the first circuit trace at the virtual timing reference plane.
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申请公布号 |
US6519747(B2) |
申请公布日期 |
2003.02.11 |
申请号 |
US20010837923 |
申请日期 |
2001.04.18 |
申请人 |
SUN MICROSYSTEMS, INC. |
发明人 |
NISHTALA SATYANARAYANA;SHENOY JAYARAMA N.;CHOU TAI-YU;FREDA MICHAEL C. |
分类号 |
G06F17/50;(IPC1-7):G06F9/45 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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