发明名称 FEEBLE SIGNAL EXTRACTING CIRCUIT
摘要 A feeble signal extracting circuit with a simple structure for extracting a feeble signal such as a pilot signal. A pilot signal extracting circuit (22) comprises a band elimination filter (BFF) (30), an analog subtracter (31), an amplifier (32), and a voltage comparator (33). The band elimination filter (30) removes only the frequency components at and near 19 kHz corresponding to the pilot signal and passes the other frequency components. The analog subtractor (31) receives a stereo composite signal inputted from an FM detecter circuit (18) and the signal produced by removing the pilot signal from the stereo composite signal by passing the stereo composite signal through the band elimination filter (30), outputs the differential signal of the two signals, and thus extracts only the pilot signal.
申请公布号 WO03010894(A1) 申请公布日期 2003.02.06
申请号 WO2002JP06401 申请日期 2002.06.26
申请人 NIIGATA SEIMITSU CO., LTD.;MIYAGI, HIROSHI 发明人 MIYAGI, HIROSHI
分类号 H04B1/16;(IPC1-7):H04B1/16 主分类号 H04B1/16
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