| 摘要 |
A system (405) employing synchronous clock signals utilizes the distribution of a fast clock signal (424,425) along a forward path to clock generators for providing standard clock signals, and a recovery of such signal via a return path (445,455). The fast clock signal has a distinguishable portion, such as a periodic missing pulse or other anomaly, which is used to determine delay characteristics for the fast clock signal to the clock generators. A controllable delay corresponding to the forward path is adjusted, based on the determined delay characteristics, to synchronize delivery of the fast clock signal to the clock generators. Preferably, a significant portion of the clock generation and distribution system is formed on a semiconductor structure have a combination of compound semiconductor material and Group IV semiconductor material. |
