发明名称 Multiple address translations
摘要 A computer system includes memory and at least a first processor that includes a memory management unit. The memory management unit includes a translation table having a plurality of translation table entries for translating processor addresses to memory addresses. The translation table entries provide first and second memory address translations for a processor address. The memory management unit can enable either the first translation or the second translation to be used in response to a processor address to enable data to be written simultaneously to different memories or parts of a memory. A first translation addresses could be for a first memory and a second translation addresses could be for a second backup memory. The backup memory could then be used in the event of a fault.
申请公布号 GB2378277(A) 申请公布日期 2003.02.05
申请号 GB20010018657 申请日期 2001.07.31
申请人 * SUN MICROSYSTEMS, INC. 发明人 PAUL * DURRANT
分类号 G06F11/20;G06F12/10;(IPC1-7):G06F12/10 主分类号 G06F11/20
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