Gain cell DRAM structure and method of producing the same

摘要

The DRAM cell arrangement has memory cells each having three transistors. The transistors are formed vertically with respect to a y axis (y) which is perpendicular to a surface (O) of a substrate (1). A gate electrode (Ga1) of the first transistor is connected to a source-drain region of the second transistor. A second source-drain (2S/D2) region of the second transistor is connected to a write bit line. A second gate (Ga2) electrode of the second transistor is connected to a write word line (WS). A third gate electrode (Ga3) of the third transistor is connected to a read word line (WA). A second source-drain region (3S/D2) of the first transistor is connected to a first source-drain region of the third transistor. A second source-drain region of the third transistor is connected to a read bit line. The first and second transistors are arranged one above the other with respect to the y axis. Also the first and third transistors are arranged one above the other with respect to the y axis.