发明名称 |
Semiconductor device including internal potential generating circuit allowing tuning in short period of time and reduction of chip area |
摘要 |
When a tuning mode signal VTUNE is activated, control clock signal TCLK is output, and counter counts up tuning signals TSIG1 to TSIG4. Tuning circuits render conductive the terminals of respective transistors, and reference potential Vref lowers in accordance with the reduction in the resistance value. When reference potential Vref attains equal to the external reference potential Ext.Vref, differential amplifier circuit stops output of the control clock signal TCLK. In accordance with the plurality of the determined tuning signals TSIG1 to TSIG4, fuse elements inside the tuning circuits are programmed.
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申请公布号 |
US6515934(B2) |
申请公布日期 |
2003.02.04 |
申请号 |
US20010986973 |
申请日期 |
2001.11.13 |
申请人 |
MITSUBISHI DENKI KABUSHIKI KAISHA |
发明人 |
KOBAYASHI MAKO;MORISHITA FUKASHI |
分类号 |
G11C5/00;G11C7/00;(IPC1-7):G11C7/00 |
主分类号 |
G11C5/00 |
代理机构 |
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地址 |
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