Incrementer/decrementer having a reduced fanout architecture

摘要

An incrementer/decrementer architecture having a reduced internal block fanout which is achieved efficiently in terms of the silicon area needed to implement the incrementer/decrementer. The incrementer/decrementer of the present invention is characterized by a modified tree structure having operators located in such a manner that the maximum internal block fanout is equal to (incrementer/decrementer width)/8 for incrementer/decrementers having a width of at least 16 bits. For incrementer/decrementers having a width of less than 16 bits, the internal block fanout is 2. The routing complexity is increased in order to implement redundant overlapping operations which, in turn, decreases the internal block fanout. However, increases in routing complexity can be accomplished within the minimum X-by-Y area of each stage of the incrementer/decrementer. Therefore, the overall performance of the incrementer/decrementer of the present invention can be optimized while meeting minimum area requirements.