| 摘要 |
PROBLEM TO BE SOLVED: To provide a dual concurrent pipeline floating point adder unit shortening arithmetic delay time in a short path. SOLUTION: The device is provided with two concurrent data paths which are the short path and a long path. In the case that a floating point arithmetic operation is a subtraction operation and an exponent difference between two operands is 0, or in the case that the floating point arithmetic operation is the subtraction operation, the exponent difference is 1 and the mantissa of the operand having a larger exponent is within the range of a predetermined number, the short path is used so as to generate the result of the floating point arithmetic operation. In the case that the floating point arithmetic operation is addition operation, or in the case that the floating point arithmetic operation is the subtraction operation and the exponent difference is larger than 1, or in the case that the floating point arithmetic operation is the subtraction operation, the exponent difference is 1 and the mantissa of the operand having the larger exponent is within the range of a different predetermined number, the long path is used so as to generate the result of the floating point arithmetic operation. |
