| 摘要 |
PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device, in which increment of layout area can be suppressed for a CAM cell, in which data is written in a plurality of memory cells, at the same time. SOLUTION: A memory cell CAMC1 is provided with a first transistor TA1 which is controlled by a first word line TWL, and which couples a first bit line ASL1 and a first internal node n1, a second transistor ZWTr controlled by a second word line WLa and coupling the first internal node n1 and a second internal node n2, an inverter INV2 for coupling the first node n1 and an input node, an inverter INV1 for coupling an output of the inverter INV2 and the input node, third and fourth transistors T11, T12 and fifth and sixth transistors T13, T14 which are connected in series respectively between a coincidence detection line MHL and a ground potential.
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