| 摘要 |
<p>PROBLEM TO BE SOLVED: To provide a memory circuit for display, the circuit configuration of which can be simplified, so that chip area of a memory for display of large capacity can be reduced, and the cost of a semiconductor integrated circuit incorporating this memory for display can be reduced. SOLUTION: Control circuits 81-84, in which a latch circuit for a segment signal is provided at a bit line end part in a memory block using conventional normal memory cells 50-53 arranged in a matrix form, at the time of access of a memory, a word line signal for display is compared with a word line signal for a memory cell for controlling these circuits; when both signals coincides, data write in the memory and data write in segment signal latch circuits 58, 59 performed are added to a memory circuit 1 for display. When both the signals coincides, since the signal is required to output as a segment signal, a segment latch signal for writing data in the segment signal latch circuits 58, 59 is generated.</p> |
