发明名称 Method of logic circuit synthesis and design using a dynamic circuit library
摘要 The circuit library available for logic synthesis is limited to a single dynamic circuit block or logic synthesis block. The circuit design method includes first defining the logic synthesis block (16) and then performing logic synthesis (17) for a predetermined logical operation to be implemented. The logic synthesis step constrained to the single logic synthesis block produces an intermediate circuit design (29) which necessarily comprises a series of dynamic circuit blocks, each associated with a single reset signal. Once the intermediate circuit (29) is produced, the circuit design method includes eliminating unnecessary devices (46) from the intermediate circuit (29) to produce a final logic circuit, and then sizing the devices (48) in the final circuit to complete the design.
申请公布号 US2003023948(A1) 申请公布日期 2003.01.30
申请号 US20010915437 申请日期 2001.07.26
申请人 DHONG SANG HOO;HOFSTEE HARM PETER;POSLUSZNY STEPHEN DOUGLAS;SILBERMAN JOEL ABRAHAM;TAKAHASHI OSAMU;WENDEL DIETER F. 发明人 DHONG SANG HOO;HOFSTEE HARM PETER;POSLUSZNY STEPHEN DOUGLAS;SILBERMAN JOEL ABRAHAM;TAKAHASHI OSAMU;WENDEL DIETER F.
分类号 G06F17/50;(IPC1-7):G06F17/50 主分类号 G06F17/50
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