| 摘要 |
A data bus architecture for integrated circuit embedded dynamic random access memory ("DRAM") having a large aspect ratio (length to width ratio) which serves to reduce power requirements in the data path through the use of multiple metal layers to reduce capacitance on the data busses. This architecture is particularly advantageous for use in addressing data bussing problems inherent in integrated circuit devices having embedded DRAM with a large aspect ratio as well as a relatively large number of input/outputs ("I/Os") which must be located along one narrow side of the memory. In accordance with the present invention, the memory is divided into multiple sections with data bussing in those sections routed in one metal, or conductive, layer. A different metal layer is used to route global data across these sections to a data register located on one edge of the memory. These global data lines are double data rate ("DDR") and single-ended (as opposed to differential-ended) which increases the physical spacing of these lines thereby reducing capacitance and power requirements. Moreover, each of the global data lines are routed to only one of the memory sections. This results in the average length of these lines being less than the length of the entire memory which further serves to reduce the capacitance of the lines.
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