发明名称 Method for on-chip testing of memory cells of an integrated memory circuit
摘要 A method for on-chip testing of memory cells of a cell array of an integrated memory circuit includes writing different data patterns to memory cells and reading the different data patterns from the memory cells in order to test the memory cells. A basic data pattern is stored in a data word register and read out by applying a data control signal provided by a controller. In addition to the basic data pattern, at least one further data pattern, which differs from the basic data pattern and is stored in a data word register section, is accessed in a targeted manner through the use of the data control signal. As a result the test proceeds rapidly and yields extensive test information.
申请公布号 US2003021169(A1) 申请公布日期 2003.01.30
申请号 US20020202690 申请日期 2002.07.24
申请人 BEER PETER;KALLSCHEUER JOCHEN;KRAUSE GUNNAR 发明人 BEER PETER;KALLSCHEUER JOCHEN;KRAUSE GUNNAR
分类号 G11C29/10;G11C29/12;(IPC1-7):G11C29/00 主分类号 G11C29/10
代理机构 代理人
主权项
地址