| 摘要 |
PROBLEM TO BE SOLVED: To suppress an increase in the number of test patterns in each functional block, regarding a semiconductor device which comprises a plurality of functional blocks. SOLUTION: The method, in which the test patterns used to verify the functional blocks, is composed of a first step, in which the relation between pins and the functional blocks of the semiconductor device is made clear; a second step in which the test patterns are sorted in units of the functional blocks; a third step in which the functional blocks to be composited are selected from information on the functional blocks; a fourth step in which the test patterns capable of being composited in the selected functional blocks to be composited are sorted; a fifth step in which the test patterns are composited in the selected functional blocks to be composited; and a sixth step in which the composited test patterns are verified. |
