| 摘要 |
PURPOSE: A circuit for controlling bit line sense amplifier is provided to control an over driving period of a sense amplifier with an optimum value after adjusting the over driving period to a test mode and performing a test operation at a wafer level. CONSTITUTION: A test mode circuit part(100) receives an address mixing signal(TA) indicating a test mode and establishes mixing values at which a test mode begin. A plurality of variable delay parts(110_1-110_n) receive an output signal of the test mode circuit part(100) and generate a plurality of delay signals that have different delay values. A multiplexor(120) selects one of output signals of the variable delay parts(110_1-110_n) and outputs a selected signal as an over driving control signal(SAP1) of a bit line sense amplifier.
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