| 摘要 |
PROBLEM TO BE SOLVED: To provide a packet transmission/reception processing circuit, in which the drop in transfer rate via a CPU is reduced when data are transferred and for which an IEEE 1394 bus can be used efficiently. SOLUTION: The circuit is provided with a packet processing circuit 112 for receiving or transmitting required information from a received packet, first and second transmission/reception FIFOs 106 and 107 for storing transmission packet data or storing reception packet data addressed to the packet processing circuit 112, a multipurpose FIFO 115 for storing transmission packet data from the CPU and reception packet data addressed to the CPU, a reception filter circuit 108 for identifying the received packet, a packet transmission circuit 103 for transferring packet data which are directly read to a link core circuit, and a packet reception circuit 104 for receiving received packet data from the link core circuit and storing it in the multipurpose FIFO 115 and the first and second transmission/reception FIFOs 106 and 107.
|
