发明名称 |
Internal clock generating circuit of semiconductor memory device and method thereof |
摘要 |
An internal clock generating circuit and method for generating an internal clock phase-synchronized to an input clock with minimum delay and at high speed is disclosed. An internal clock generating circuit comprises a first delay control circuit for generating a first clock having the time delay of up to T/2 (where T is a cycle of an input clock) from the input clock and for generating a first variable delay control signal; and a second delay control circuit for generating a second clock in response to the first variable delay control signal, the second clock having the time delay of greater than T/2 from the input clock at an initial state and having the time delay of about T from the input clock in a phase-locked state.
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申请公布号 |
US2003016063(A1) |
申请公布日期 |
2003.01.23 |
申请号 |
US20020072487 |
申请日期 |
2002.02.07 |
申请人 |
SAMSUNG ELECTRONICS CO., LTD. |
发明人 |
PARK JUNG-WOO;CHO UK-RAE;KIM NAM-SEOG |
分类号 |
G06F1/10;G06F1/06;G11C8/00;H03K5/06;H03K5/135;H03L7/07;H03L7/081;(IPC1-7):H03L7/06 |
主分类号 |
G06F1/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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