发明名称 WIRING BOARD OF MULTIPLE ALLOCATION
摘要 <p>PROBLEM TO BE SOLVED: To provide a wiring board of multiple allocation, on which electrical checks of wiring board regions can be performed efficiently, while the regions are arranged on a mother substrate. SOLUTION: In the mother substrate 1, constituted by laminating a plurality of insulation layers 1a and 1b upon another of this wiring board of multiple allocation, many wiring board regions 2, each having a recessed section 2a for housing electronic parts and a plurality of wiring conductors 3 electrically connected with the electrodes of the electronic components on its upper surface side are arranged. In addition, a plurality of connecting conductors 4 for plating which electrically connect the wiring conductors 3 to each other beyond the boundaries of the wiring board regions 2 are provided between the insulating layers 1a and 1b. On the upper surface of the mother substrate 1, moreover, recessed sections 2b are provided, to partially expose the connecting conductors 4.</p>
申请公布号 JP2003017816(A) 申请公布日期 2003.01.17
申请号 JP20010195873 申请日期 2001.06.28
申请人 KYOCERA CORP 发明人 NAKAMOTO KOTARO
分类号 H05K1/02;H01L23/12;H05K3/00;H05K3/46;(IPC1-7):H05K1/02 主分类号 H05K1/02
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