发明名称 DELAY CIRCUIT AND TEST DEVICE
摘要 <p>PROBLEM TO BE SOLVED: To provide a delay circuit with a small delay error. SOLUTION: This invention provides the delay circuit for delaying a given input signal on the basis of a delay setting value and providing an output is characterized in to comprise a delay section comprising a plurality of delay elements, a storage section for storing supply position data for denoting to which of a plurality of the delay elements in cascade connection the input signal is to be supplied corresponding respectively to each of a plurality of predetermined delay setting values, and a selection section for selecting to which of a plurality of the delay elements the input signal is to be supplied based on the delay setting values and the supply position data.</p>
申请公布号 JP2003017988(A) 申请公布日期 2003.01.17
申请号 JP20010198359 申请日期 2001.06.29
申请人 ADVANTEST CORP 发明人 SUDA MASAKATSU
分类号 G01R31/28;H03K5/14;(IPC1-7):H03K5/14 主分类号 G01R31/28
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